计算机系统体系结构 第3版【2025|PDF下载-Epub版本|mobi电子书|kindle百度云盘下载】

计算机系统体系结构 第3版PDF格式电子书版下载

注意：本站所有压缩包均有解压码： 点击下载压缩包解压工具

CHAPTER ONE Digital Logic Circuits1

1-1 Digital Computers1

1-2 Logic Gates4

1-3 Boolean Algebra7

Complement of a Function10

1-4 Map Simplification11

Product-of-Sums Simplification14

Don＇t-Care Conditions16

1-5 Combinational Circuits18

Half-Adder19

Full-Adder20

1-6 Flip-Flops22

SR Flip-Flop22

D Flip-Flop23

JK Flip-Flop24

T Flip-Flop24

Edge-Triggered Flip-Flops25

Excitation Tables27

1-7 Sequential Circuits28

Flip-Flop Input Equations28

State Table30

State Diagram31

Design Example32

Design Procedure36

Problems37

References39

CHAPTER TWO Digital Components41

2-1 Integrated Circuits41

2-2 Decoders43

NAND Gate Decoder45

Decoder Expansion46

Encoders47

2-3 Multiplexers48

2-4 Registers50

Register with Parallel Load51

2-5 Shift Registers53

Bidirectional Shift Register with Parallel Load53

2-6 Binary Counters56

Binary Counter with Parallel Load58

2-7 Memory Unit58

Random-Access Memory60

Read-Only Memory61

Types of ROMs62

Problems63

References65

CHAPTER THREE Data Representation．67

3-1 Data Types67

Number Systems68

Octal and Hexadecimal Numbers69

Decimal Representation72

Alphanumeric Representation73

3-2 Complements74

(r-1) s Complement75

(r s)Complement75

Subtraction of Unsigned Numbers76

3-3 Fixed-Point Representation77

Integer Representation78

Arithmetic Addition79

Arithmetic Subtraction80

Overflow80

Decimal Fixed-Point Representation81

3-4 Floating-Point Representation83

3-5 Other Binary Codes84

Gray Code84

Other Decimal Codes85

Other Alphanumeric Codes86

3-6 Error Detection Codes87

Problems89

References91

CHAPTER FOUR Register Transfer and Microoperations93

4-1 Register Transfer Language93

4-2 Register Transfer95

4-3 Bus and Memory Transfers97

Three-State Bus Buffers100

Memory Transfer101

4-4 Arithmetic Microoperations102

Binary Adder103

Binary Adder-Subtractor104

Binary Incrementer105

Arithmetic Circuit106

4-5 Logic Microoperations108

List of Logic Microoperations109

Hardware Implementation111

Some Applications111

4-6 Shift Microoperations114

Hardware Implementation115

4-7 Arithmetic Logic Shift Unit116

Problems119

References122

CHAPTER FIVE Basic Computer Organization and Design123

5-1 Instruction Codes123

Stored Program Organization125

Indirect Address126

5-2 Computer Registers127

Common Bus System129

5-3 Computer Instructions132

Instruction Set Completeness134

5-4 Timing and Control135

5-5 Instruction Cycle139

Fetch and Decode139

Determine the Type of Instruction141

Register-Reference Instruction143

5-6 Memory-Reference Instructions145

AND to AC145

ADD to AC146

LDA: Load to AC146

STA: Store AC147

BUN: Branch Unconditionally147

BSA: Branch and Save Return Address147

ISZ: Increment and Skip If Zero149

Control Flowchart149

5-7 Input-Output and Interrupt150

Input-Output Configuration151

Input-Output Instructions152

Program Interrupt153

Interrupt Cycle156

5-8 Complete Computer Description157

5-9 Design of Basic Computer157

Control Logic Gates160

Control of Registers and Memory160

Control of Single Flip-Flops162

Control of Common Bus162

5-10 Design of Accumulator Logic164

Control of AC Register165

Adder and Logic Circuit166

Problems167

References171

CHAPTER SIX Programming the Basic Computer173

6-1 Introduction173

6-2 Machine Language174

6-3 Assembly Language179

Rules of the Language179

An Example181

Translation to Binary182

6-4 The Assembler183

Representation of Symbolic Program in Memory184

First Pass185

Second Pass187

6-5 Program Loops190

6-6 Programming Arithmetic and Logic Operations192

Multiplication Program193

Double-Precision Addition196

Logic Operations197

Shift Operations197

6-7 Subroutines198

Subroutines Parameters and Data Linkage200

6-8 Input-Output Programming203

Character Manipulation204

Program Interrupt205

Problems208

References211

CHAPTER SEVEN Microprogrammed Control213

7-1 Control Memory213

7-2 Address Sequencing216

Conditional Branching217

Mapping of Instruction219

Subroutines220

7-3 Microprogram Example220

Computer Configuration220

Microinstruction Format222

Symbolic Microinstructions225

The Fetch Routine226

Symbolic Microprogram227

Binary Microprogram229

7-4 Design of Control Unit231

Microprogram Sequencer232

Problems235

Reference238

CHAPTER EIGHT Central Processing Unit241

8-1 Introduction241

8-2 General Register Organization242

Control Word244

Examples of Microoperations246

8-3 Stack Organization247

Register Stack247

Memory Stack249

Reverse Polish Notation251

Evaluation of Arithmetic Expressions253

8-4 Instruction Formats255

Three-Address Instructions258

Two-Address Instructions258

One--Address Instructions259

Zero--Address Instructions259

RISC Instructions259

8-5 Addressing Modes260

Numerical Example264

8-6 Data Transfer and Manipulation266

Data Transfer Instructions267

Data Manipulation Instructions268

Arithmetic Instructions269

Logical and Bit Manipulation Instructions270

Shift Instructions271

8-7 Program Control273

Status Bit Conditions274

Conditional Branch Instructions275

Subroutine Call and Return278

Program Interrupt279

Types of Interrupts281

8-8 Reduced Instruction Set Computer (RISC)282

CISC Characteristics283

RISC Characteristics284

Overlapped Register Windows285

Berkeley RISC 1288

Problems291

References297

CHAPTER NINE Pipeline and Vector Processing299

9-1 Parallel Processing299

9-2 Pipelining302

General Considerations304

9-3 Arithmetic Pipeline307

9-4 Instruction Pipeline310

Example: Four-Segment Instruction Pipeline311

Data Dependency313

Handling of Branch Instructions314

9-5 RISC Pipeline315

Example: Three-Segment Instruction Pipeline316

Delayed Load317

Delayed Branch318

9-6 Vector Processing319

Vector Operations321

Matrix Multiplication322

Memory Interleaving324

Supercomputers325

9-7 Array Processors326

Attached Array Processor326

SIMD Array Processor327

Problems329

References330

CHAPTER TEN Computer Arithmetic333

10-1 Introduction333

10-2 Addition and Subtraction334

Addition and Subtraction with Signed-Magnitude Data335

Hardware Implementation336

Hardware Algorithm337

Addition and Subtraction with Signed-Z s Complement Data338

10-3 Multiplication Algorithms340

Hardware Implementation for Signed-Magnitude Data341

Hardware Algorithm342

Booth Multiplication Algorithm343

Array Multiplier346

10-4 Division Algorithms348

Hardware Implementation for Signed-Magnitude Data349

Divide Overflow351

Hardware Algorithm352

Other Algorithms353

10-5 Floating-Point Arithmetic Operations354

Basic Considerations354

Register Configuration357

Addition and Subtraction358

Multiplication360

Division362

10-6 Decimal Arithmetic Unit363

BCD Adder365

BCD Subtraction368

10-7 Decimal Arithmetic Operations369

Addition and Subtraction371

Multiplication371

Division374

Floating-Point Operations376

Problems376

References380

CHAPTER ELEVEN Input-Output Organization381

11-1 Peripheral Devices381

ASCII Alphanumeric Characters383

11-2 Input-Output Interface385

I/O Bus and Interface Modules386

I/O versus Memory Bus387

Isolated versus Memory-Mapped I/O388

Example of I/O Interface389

11-3 Asynchronous Data Transfer391

Strobe Control391

Handshaking393

Asynchronous Serial Transfer396

Asynchronous Communication Interface398

First-In, First-Out Buffer400

11-4 Modes of Transfer402

Example of Programmed I/O403

Interrupt-Initiated I/O406

Software Considerations406

11-5 Priority Interrupt407

Daisy-Chaining Priority408

Parallel Priority Interrupt409

Priority Encoder411

Interrupt Cycle412

Software Routines413

Initial and Final Operations414

11-6 Direct Memory Access (DMA)415

DMA Controller416

DMA Transfer418

11-7 Input-Output Processor (IOP)420

CPU-IOP Communication422

IBM 370 I/O Channel423

Intel 8098 IOP427

11-8 Serial Communication429

Character-Oriented Protocol432

Transmission Example433

Data Transparency436

Bit-Oriented Protocol437

Problems439

References442

CHAPTER TWELVE Memory Organization445

12-1 Memory Hierarchy445

12-2 Main Memory448

RAM and ROM Chips449

Memory Address Map450

Memory Connection to CPU452

12-3 Auxiliary Memory452

Magnetic Disks454

Magnetic Tape455

12-4 Associative Memory456

Hardware Organization457

Match Logic459

Read Operation460

Write Operation461

12-5 Cache Memory462

Associative Mapping464

Direct Mapping465

Set-Associative Mapping467

Writing into Cache468

Cache Initialization469

12-6 Virtual Memory469

Address Space and Memory Space470

Address Mapping Using Pages472

Associative Memory Page Table474

Page replacement475

12-7 Memory Management Hardware476

Segmented-Page Mapping477

Numerical Example479

Memory Protection482

Problems483

References486

CHAPTER THIRTEEN Multiprocessors489

13-1 Characteristics of Multiprocessors489

13-2 Interconnection Structures491

Time-Shared Common Bus491

Multiport Memory493

Crossbar Switch494

Multistage Switching Network496

Hypercube Interconnection498

13-3 Interprocessor Arbitration500

System Bus500

Serial Arbitration Procedure502

Parallel Arbitration Logic503

Dynamic Arbitration Algorithms505

13-4 Interprocessor Communication and Synchronization506

Interprocessor Synchronization507

Mutual Exclusion with a Semaphore508

13-5 Cache Coherence509

Conditions for Incoherence509

Solutions to the Cache Coherence Problem510

Problems512

References514

Index515